In high-speed serial transfer, since data is superposed on a clock, in order to accurately separate the data and the clock, scramble processing is performed on the transmission data so as to avoid the periodicity of the data (i.e., continuation of the same pattern of data) in the data reception device. Therefore, the data reception device performs descramble processing on the received data.
As a conventional data reception device, Patent Document 1 describes a data reception device capable of initializing a descramble circuit even when a symbol for initialization such as a COM symbol and timing adjustment data such as a SKP symbol are partially damaged due to the influence of noise on a channel. Note that the PCI Express (Peripheral Component Interconnect Express) bus system is used as an example here.
FIG. 10 is a block diagram schematically showing the configuration of a data transfer device using the PCI Express bus system to which the technology described in Patent Document 1 is not applied.
Transmission data is supplied to a data transmission device (including a scramble circuit 101, an 8B/10B encoder circuit 102, and a P/S conversion circuit 103) in the data transfer device, and is scrambled by the scramble circuit 101. Next, the 8B/10B encoder circuit 102 encodes the 8-bit data into 10-bit data so that data of “0” or “1” do not successively occur a predetermined number or more of times. Then, the P/S conversion circuit 103 converts the parallel data into serial data, and the data is transmitted to a differential transmission Lane 104.
Further, data received from a differential reception path (Lane) 105 is supplied to a data reception device (including an S/P conversion circuit 106, an elastic buffer circuit 107, an 8B/10B decoder circuit 108, and a descramble circuit 110) in the data transfer device and is converted from serial data into parallel data by the S/P conversion circuit 106. Then the elastic buffer circuit 107 corrects the clock frequency deviation between the transmitter and the receiver, the 8B/10B decoder circuit 108 decodes the 10-bit data into 8-bit data, and the descramble circuit 110 descramble the data.
In the PCI Express bus system as described, the scramble processing by the scramble circuit 101 and the descramble processing by the descramble circuit 110 are performed by circuits using linear feedback shift registers (LFSR).
To the scramble circuit 101 and the descramble circuit 110, the following rules are applied: the shift register is initialized to an initialized value (FFFh) with a COM symbol and the LFSR shifts, except for when a SKP symbol is received (the LFSR does not shift when a SKP symbol is received); all D codes except those within a Training Sequence and a Compliance Pattern are scrambled and descrambled; and all K codes are not scrambled or descrambled.
The COM symbol is a symbol for initialization, which is data for initializing the scramble circuit 101 and the descramble circuit 110. Further, the SKP symbol is timing adjustment data for correcting the clock frequency deviation between the transmitter side and the receiver side without having the LFSRs shift in the scramble circuit 101 and the descramble circuit 110. Moreover, the K codes are twelve kinds of special data that are not normal data and the K codes include the aforementioned COM symbol and SKP symbol. The D codes are data symbols that are not control data such as the K codes.
In the PCI Express bus system, a timing adjustment data set (SKP ordered set) is inserted at a regular interval (at every 1080 to 1156 symbols) during an idle time of data transmission (D0.0, i.e., a D code 00h is transmitted). The SKP ordered set is one COM symbol followed by three SKP symbols. The clock frequency deviation is corrected by increasing or decreasing the number of the SKP symbols in the SKP ordered set in the elastic buffer circuit 107.
In other words, when the frequency of the receiver side is greater than that of the transmitter side, the Physical Layer of the receiver increases the number of SKP symbols included in the SKP ordered set and hands it to the Link Layer. On the other hand, when the frequency of the transmitter side is greater than that of the receiver side, the Physical Layer of the receiver side decreases the number of SKP symbols included in the SKP ordered set and hands it to the Link Layer.
As described above, the LFSRs in the scramble circuit 101 and the descramble circuit 110 are initialized by the COM symbol. Since the SKP symbol may be added or deleted by the receiver, the LFSRs in the scramble circuit 101 and the descramble circuit 110 do not operate in response to it. In other words, the LFSRs in the scramble circuit 101 and the descramble circuit 110 operate in response to data other than the SKP symbols.
However, in the data transfer device described above, when the received data is damaged and therefore the device is unable to receive the COM symbol, the LFSR in the descramble circuit 110 cannot be initialized and the value of the LFSR deviates from the value of the LFSR in the scramble circuit 101 of the transmitter. Further, when the SKP symbol is damaged and turned into different data, the LFSR in the descramble circuit 110 shifts, although it is not supposed to shift, the values of the LFSRs in the transmitter side and the receiver side deviate from each other, and the device is unable to receive accurate data.
In order to solve this problem, the data reception device described in Patent Document 1 is designed so that the descramble circuit can be initialized even when a symbol for initialization such as the COM symbol and timing adjustment data such as the SKP symbol are partially damaged.
FIG. 11 is a block diagram schematically showing the configuration of the data transfer device described in Patent Document 1. As shown in FIG. 11, a data reception device in the data transfer device described in Patent Document 1 comprises an elastic buffer circuit 107 that receives a signal received from a reception Lane and adjusts the clock frequency of the transmitter side, and a descramble circuit 110 that descrambles an output signal of the elastic buffer circuit 107. In the data reception device described in Patent Document 1, the received signal has a COM symbol that initializes the descramble circuit 110 and a plurality of SKP symbols arranged so as to follow the COM symbol as a data set in a data stream, and a SKP/COM conversion circuit 109 that converts the timing adjustment data in the data set into the initialization data is provided between the elastic buffer circuit 107 and the descramble circuit 110.
FIG. 12A is a drawing for explaining an example of input data the scramble circuit in the data reception device described in Patent Document 1; and LFAR; FIG. 12B is a drawing for explaining an example of output data from the 8B/10B decoder circuit; and FIG. 12C is a drawing for explaining an example of input data to the descramble circuit, and the LFSR. As shown in FIG. 12B, let's assume that an error has occurred on the first SKP symbol in the SKP ordered set in a communication channel in the data generated as shown in FIG. 12A. In this case, the data reception device described in Patent Document 1 replaces all the SKP symbols with COM symbols before descrambling, as shown in FIG. 12C. As a result, the descramble circuit 110 repeats the initialization for the same number of times as the number of the COM symbols replacing the SKP symbols even when an error occurs only on one SKP symbol. In other words, the initialization is reliably performed and it becomes possible to make sure that the descramble processing on the receiver's side corresponds to the scramble processing on the transmitter's side.
[Patent Document 1]
    Japanese Patent Kokai Publication No. JP2005-268910A